1. Technical Field
This disclosure relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device having a fuse pattern and methods of fabricating the same.
2. Discussion of the Related Art
Semiconductor memory devices formed on a semiconductor substrate are electrically tested prior to an assembly process. As a result, semiconductor memory devices are classified as bad chips or good chips. When a chip includes at least one bad cell, the bad cell may be replaced with a redundant cell though a repair process. The repair process includes a laser beam irradiation operation blowing predetermined fuses such that the redundant cell has an address of the bad cell in a write mode and a read mode. The fuses are generally formed, concurrently with a bit line or an interconnection pattern within a semiconductor memory device.
Because of the current high-density integration and multi-layer structure of a semiconductor device, the thickness of an oxide layer to be etched to form a fuse window is larger than in the past. Thus, it is difficult to form a fuse and a bit line concurrently. Research has been conducted for a metal fuse to be formed at the same time of forming the interconnection pattern. To lower the resistance, the interconnection pattern is formed to be greater in thickness than the bit line. Thus, since the metal fuse patterned and formed with the interconnection pattern concurrently is also formed with a thickness greater than that of the bit line fuse, a high energy is required for blowing the metal fuse. After blowing the metal fuse, the residual matter of the metal fuse may cause a bridge with an adjacent metal fuse due to the thick thickness of the metal fuse. As a result, there remains a need for a thinner metal fuse to reduce the chance of a bridge forming with adjacent metal fuses and to reduce the energy required for blowing the fuse.
FIGS. 1A through 1D are cross-sectional views for explaining a method of fabricating a conventional semiconductor device. In FIGS. 1A through 1D, the portions indicated by reference numbers “I0”, “F0” and “P0” represent an interconnection region, a fuse region and a pad region, respectively.
Referring to FIG. 1A, a first interlayer insulating layer 115 is formed on a semiconductor substrate 110. A barrier layer 120, a conductive layer 123 and a capping layer 125 are sequentially formed on the first interlayer insulating layer 115. The barrier layer 120 can be formed of a titanium nitride layer, or a titanium layer and a titanium nitride layer, which are sequentially stacked. The conductive layer 123 is formed of an aluminum layer. The capping layer 125 can be formed of a titanium layer, or a titanium layer and a titanium nitride layer, which are sequentially stacked.
Referring to FIG. 1B, preliminary fuse patterns 127a are formed of a barrier pattern 120a, a conductive pattern 123a, and a capping pattern 125a, which are sequentially stacked within the fuse region F0 by patterning the capping layer 125, the conductive layer 123 and the barrier layer 120 sequentially. Similarly, first interconnection patterns 127b include a barrier pattern 120b, a conductive pattern 123b, and a capping pattern 125b, which are sequentially stacked within the interconnection region I0.
A second interlayer insulating layer 133 is formed on the semiconductor substrate 110 having the preliminary fuse patterns 127a and the first interconnection patterns 127b. Via contact plugs 134 may be formed to penetrate the second interlayer insulating layer 133, and to be electrically connected with the first interconnection patterns 127b. An upper barrier layer, an upper conductive layer and an upper capping layer are sequentially formed on the substrate having the via contact plugs 134. Second interconnection patterns 140 are formed on the second interlayer insulating layer 133 within the interconnection region I0, by patterning the upper capping layer, the upper conductive layer and the upper barrier layer in turn, and concurrently, a pad 140p is formed on the second interlayer insulating layer 133 within the pad region P0.
Each of the second interconnection patterns 140 may be formed of an upper barrier pattern 135, an upper conductive pattern 137, and an upper capping pattern 139, which are sequentially stacked. The second interconnection patterns 140 are electrically connected with the first interconnection patterns 127b respectively, through the via contact plugs 134. The pad 140p includes a pad conductive pattern 138p and a pad capping pattern 139p, which are sequentially stacked, and the pad conductive pattern 138p is formed of a pad barrier pattern 135p and a pad conductive pattern 137p, which are sequentially stacked.
A passivation layer 143 is formed on the substrate having the second interconnection patterns 140 and the pad 140p. The passivation layer 143 may include a plasma oxide layer 141 and a plasma nitride layer 142, which are sequentially stacked.
Referring to FIG. 1C, a fuse window 145f exposing the capping patterns 125a is formed by etching the passivation layer 143 within the fuse region F0 and partially etching the second interlayer insulating layer 133 positioned below the passivation layer 143, by using a photolithograph process and an etch process. Then, fuse patterns 127a′ which are thinner in thickness than the preliminary fuse patterns 127a are formed by etching and removing the exposed capping patterns 125a and partially etching the conductive patterns 123a positioned below the capping patterns 125a. Each of the fuse patterns 127a′ is formed of the barrier pattern 120a and the partially etched conductive pattern 123a′, which are sequentially stacked. Concurrently, a pad window 145p exposing the pad conductive pattern 138p is formed by sequentially etching predetermined portions of the passivation layer 143 and the pad capping pattern 139p within the pad region P0. At this time, the pad conductive pattern 137p may be partially etched.
A conformal fuse protecting layer 147 is formed on the substrate having the fuse patterns 127a′. As a result, the fuse protecting layer 147 is formed to cover the whole surfaces of the upper surface of the passivation layer 143, the inside of the fuse window 145f and the inside of the pad window 145p. The fuse protecting layer 147 may include a silicon nitride layer. The fuse protecting layer 147 is formed to protect the exposed fuse patterns 127a′. 
Referring to FIG. 1D, the pad conductive pad 138p positioned below the pad window 145p is exposed by selectively patterning the fuse protecting layer 147. Then, a polyimide layer is formed on the substrate where the pad conductive pattern 138p is exposed, and a polyimide pattern 150 having a fuse window opening 150f and a pad window opening 150p to expose the fuse window 145f and the pad window 145p, respectively, is formed by an exposure process and a developing process. The semiconductor device is electrically tested prior to the assembly process, and as a result, with respect to bad cells, a laser beam is irradiated through the fuse window opening 150f and the fuse window 145f for the repair process. Then, in the assembly process, a pad bonding work is performed through the pad window opening 150p and the pad window 145p. 
According to the above-described related art, the preliminary fuse patterns 127a may be unevenly etched while the second interlayer insulating layer 133 is etched. As a result, as shown in FIG. 1C, the upper surface of the fuse patterns 127a′ may not be even by the non-uniform etching and may be uneven in thickness. Furthermore, the thickness of the fuse patterns 127a′ may be different from each other in a wafer, because of the non-uniform etching of the preliminary fuse patterns 127a. For example, a fuse pattern A0 may be greater in thickness that a fuse pattern B0. As a result, when the same energy is used for blowing the fuse patterns, the fuse pattern B0 is blown. However, a residual pattern may exist with respect to the fuse pattern A0 because the fuse pattern A0 is greater in thickness than the fuse pattern B0.
Furthermore, as the fuse protecting layer 147 is formed after the fuse patterns 127a′ are formed, a photoresist process is added to expose the pad conductive pattern 138p. The process of forming the polyimide pattern 150 is also separately performed. Consequently, since the processes with respect to the fuse window, the pad window and the polyimide pattern are separately performed, the photolithography process is performed three times, thereby increasing production costs.
Thus, there remains a need for a method of fabricating a semiconductor device having a fuse pattern, each pattern having a flat upper surface and improving a thickness uniformity of the fuse patterns in a wafer and simplifying the photolithography process.